Circuit board and method for manufacturing the same

ABSTRACT

The present application provides a circuit board and a manufacturing method therefor. The circuit board includes: a core board, at least one chip, a first circuit layer, and a first insulating layer. A groove body is formed on the core board. The chip is provided in the groove body. The chip is provided with a first lead-out terminal. The first circuit layer is provided on at least one side of the core board. The first insulating layer is provided between the core board and the first circuit layer. The first lead-out terminal passes through the first insulating layer and is connected to the first circuit layer, so that the chip is electrically connected to the first circuit layer. Thus, the wiring between the chip and the circuit is more flexible.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-application of International (PCT) Patent Application No. PCT/CN2020/127022, filed on Nov. 6, 2020, which claims priority of Chinese Patent Application No. 20911158137.9, filed on Nov. 22, 2019, in China National Intellectual Property Administration, the entire contents of which are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to the field of chip embedding, and in particular to a circuit board and a method of manufacturing a circuit board.

BACKGROUND

In the art, electronic packaging does not only provide protection for a chip, but also needs to meet increasing requirements for performance, reliability, heat dissipation and power distribution, with a certain cost. An increase in a speed and a processing power of a functional chip requires more pins, a faster clock frequency and better power distribution. At the same time, since users have increasing demands for smart mobile electronic devices, which are ultra-thin, miniaturized, multi-functional, and have high performance and low power consumption, integration of computing and communication functions in mobile terminal chips is formed. A trend towards a chip having higher integration, higher complexity, lower power consumption and lower costs has occurred.

SUMMARY OF THE DISCLOSURE

According to an aspect, the present disclosure provides a circuit board. The circuit board includes: a core board, defining a groove; at least one chip, received in the groove, wherein the chip has a first lead terminal; a first circuit layer, arranged on at least one side of the core board; a first insulating layer, disposed between the core board and the first circuit layer. The first lead terminal extends through the first insulating layer to be connected to the first circuit layer, enabling the chip to be electrically connected to the first circuit layer.

According to another aspect of the present disclosure, a method of manufacturing the circuit board is provided and includes: providing a core board; defining a groove in the core board; placing a chip in the groove and exposing a first lead terminal; defining a first through hole in a first insulating layer at a position corresponding to the first lead terminal; and arranging the first insulating layer and the first circuit layer successively on at least one side of the core board, allowing the first lead terminal to extend through the first through hole to be electrically connected to the first circuit layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to illustrate more clearly technical solutions in the embodiments of the present disclosure, the accompanying drawings used for the description of the embodiments is described in brief. Apparently, the following drawings are only some of the embodiments of the present disclosure, and other drawings may be obtained by any ordinary skilled person in the art based on these drawings without any creative effort.

FIG. 1 is a structural schematic view of a circuit board according to a first embodiment of the present disclosure.

FIG. 2 is a structural schematic view of a circuit board according to a second embodiment of the present disclosure.

FIG. 3 is a structural schematic view of a circuit board according to a third embodiment of the present disclosure.

FIG. 4 is a structural schematic view of a circuit board according to a fourth embodiment of the present disclosure.

FIG. 5 is a flow chart of a method of manufacturing a circuit board according to a first embodiment of the present disclosure.

FIG. 6 is a flow chart of a method of manufacturing a circuit board according to a second embodiment of the present disclosure.

DETAILED DESCRIPTION

Technical solutions in the embodiments of the present disclosure will be clearly and completely described below by referring to the accompanying drawings in the embodiments of the present disclosure. Apparently, the embodiments described are only a part, but not all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by any ordinary skilled person in the art without any creative work shall fall within the scope of protection of the present disclosure.

As shown in FIG. 1, FIG. 1 is a structural schematic view of a circuit board according to a first embodiment of the present disclosure. The circuit board includes: a core board 11, a chip 13, a first insulating layer 15, a first circuit layer 16. The core board 11 defines a groove 12. The chip 13 is received in the groove 12. In an embodiment, the chip 13 may include a camera chip for photographing, a fingerprint chip for photo-sensitive fingerprint recognition, a speaker chip and so on, which will not be limited by the present disclosure. The chip 13 has a first lead terminal 14. In an embodiment, each of two surfaces of the chip 13 has the first lead terminal 14. In another embodiment, only one surface of the chip 13 has the first lead terminal 14. The first lead terminal 14 may be a copper post or a conductive through-hole. The first circuit layer 16 is arranged on each of two opposite surfaces of the core board 11. The first insulating layer 15 is disposed between the core board 11 and the first circuit layer 16 to bond the first circuit layer 16 to the core board 11.

The core board 11 is a copper-clad board, which is a basic material for manufacturing the circuit board. The copper-clad board includes a substrate board and a copper clad disposed on and covering the substrate board. The substrate board is a plurality of bonding sheets. Each of the plurality of bonding sheets is made by dipping a paper substrate, a glass fiber substrate, a synthetic fiber substrate, a non-woven substrate, a composite substrate and other materials in resin. The copper clad is coating on one side or two sides of the substrate board, and hot-press curing is performed, obtaining the copper-clad board. In an embodiment, the copper clad on each of two surfaces of the core board 11 may or may not have a circuit pattern layer, which may be determined based on demands and will not be limited by the present disclosure.

The first insulating layer 15 defines a through-hole (not shown) at a position corresponding to the first lead terminal 14 of the chip 13. The first lead terminal 14 extends through the through-hole to be electrically connected to the first circuit layer 16. When the first lead terminal 14 is the copper post, electroplating may be carried out directly at a predetermined position of the chip 13. When the first lead terminal 14 is the conductive through-hole, a through-hole may be defined at a predetermined position of the first insulating layer 15, and a side wall of the through-hole is electroplated, such that a conductive layer is formed.

In the present embodiment, when one first lead terminal 14 is arranged on the chip 13, the first circuit layer 16 has one first circuit network. When a plurality of first lead terminals 14 are arranged on the chip 13, the first circuit layer 16 has a plurality of first circuit networks. The plurality of first circuit networks are independent of each other, and the plurality of first lead terminals 14 connect the chip 13 to different first circuit networks respectively.

In the present embodiment, the groove 12 in the core board 11 is a groove extending through two surfaces of the core board 11. When receiving the chip 13 in the groove 12, a distance between the chip 13 and a side wall of the groove 12 is 20 μm-50 μm, and a molding silicone is disposed between the chip 13 and the side wall of the groove 12. The molding silicone is a colourless and transparent liquid and can be sulphurated at a temperature above 150° C. When the molding silicone is cured, the cured molding silicone is permeable and elastic to some extent. The cured molding silicone has temperature resistance, weather resistance, electrical insulation, physiological inertness, a low surface tension and a low surface energy. Filling the groove with the molding silicone bonds the chip 13 to the core board 11.

In an embodiment, a thickness of the first insulating layer 15 is 10 μm-40 μm, and a thickness of the first circuit layer 16 is 10 μm-40 μm. In detail, the thickness of the first insulating layer 15 is 30 μm, and the thickness of the first circuit layer 16 is 18 μm. The first circuit layer 16 is obtained by making a circuit pattern on a copper layer. The first insulating layer 15 is a curable adhesive substance. In detail, the first insulating layer 15 is a semi-cured sheet, serving as a bonding layer disposed between layers while laminating. In detail, the semi-cured sheet mainly consists of resin and reinforcing material. While producing multiple layers of the circuit board, usually the glass fiber cloth may be taken as the reinforcing material. The glass fiber cloth may be soaked with resin gel, and a heat treatment is performed to pre-bake the soaked cloth into a sheet. The sheet may be softened under heating and pressure, and may be cured and viscous after being cooled. In a high-temperature pressing process, the viscous sheet can bond to adjacent two layers. That is, the first insulation layer 15 is melted when being pressed at a high temperature to bond the first circuit layer 16 to the core board 11.

In an embodiment, a side wall of the groove 12 that receives the chip 13 is arranged with a metal layer. While the circuit board is operating, the metal layer can conduct heat generated by the chip 13 to the core board 11. In a specific embodiment, the first insulating layer 15 corresponding to the core board 11 can also define the conductive hole, such that the heat generated by the chip 13 can be transferred to the first circuit layer 16, and the heat can be dissipated. In this way, the chip 13 may be protected better, and a service life of the chip 13 may be extended.

As shown in FIG. 2, FIG. 2 is a structural schematic view of a circuit board according to a second embodiment of the present disclosure. In the present embodiment, the groove 12 for receiving the chip 13 is a blind groove running through one surface of the core board 11. In the present embodiment, the first circuit layer 16 is arranged on one surface of the core board 11, and the first insulation layer 15 is disposed between the core board 11 and the first circuit layer 16.

It shall be understood that the surface of the chip 13 has the first lead terminal 14. In detail, the first lead terminal is located on a side where the first circuit layer 16 is arranged.

As shown in FIG. 3, FIG. 3 is a structural schematic view of a circuit board according to a third embodiment of the present disclosure. In the present embodiment, a second insulating layer 17 and a second circuit layer 18 are successively disposed on an outer side of the first circuit layer 16. The second insulating layer 17 defines a through-hole at a predetermined location. Conductive material is received in the through-hole to form a second lead terminal 19. The second lead terminal 19 is configured to electrically connect the first circuit layer 16 to the second circuit layer 18.

It shall be understood that the second lead terminal 19 electrically connects the first circuit layer 16 to the second circuit layer 18, further enabling the chip 13 to be electrically connected to the second circuit layer 18. In an embodiment, when one first circuit network is arranged on the first circuit layer 16, the chip 13 has one first lead terminal 14. When a plurality of first circuit networks are arranged on the first circuit layer 16, the chip 13 has a plurality of first lead terminals 14. In detail, the number of first lead terminals 14 corresponds to the number of first circuit networks. In an embodiment, when one first circuit network is arranged on the first circuit layer 16, and one second circuit network is arranged on the second circuit layer 18, one first lead terminal 14 and one second lead terminal 19 are arranged. The number of first lead terminals 14 corresponds to the number of second lead terminals 19, when a plurality of first circuit networks are arranged on the first circuit layer 16, a plurality of second circuit networks are arranged on the second circuit layer 18, and the number of the first circuit networks on the first circuit layer 16 is equal to the number of the second circuit networks on the second circuit layer 18. When the number of second circuit networks on the second circuit layer 18 is n times of the number of first circuit networks on the first circuit layer 16, the number of second lead terminals 19 is n times the number of first lead terminals 14.

In an embodiment, in order to improve a signal transmission efficiency of the first lead terminal 14 and the second lead terminal 19, a pad is arranged on each of an end of the first lead terminal 14 connected to the chip 13 and an end of the first lead terminal 14 connected to the first circuit layer 16. Further, another pad is arranged on each of an end of the second lead terminal 19 connected to the first circuit layer 16 and an end of the second lead terminal 19 connected to the second circuit layer 18.

In an embodiment, a thickness of the second insulating layer 17 is 10 μm-40 μm, and a thickness of the second circuit layer 18 is 10 μm-40 μm. In detail, the thickness of the second insulating layer 17 is 30 μm, and the thickness of the second circuit layer 18 is 18 μm. The second circuit layer 18 is obtained by making a circuit pattern on the copper layer. The second insulating layer 17 is a curable adhesive substance. In detail, the second insulating layer 17 is a semi-cured sheet, serving as a bonding layer disposed between layers while laminating. In detail, the semi-cured sheet mainly consists of resin and reinforcing material. While producing multiple layers of the circuit board, usually the glass fiber cloth may be taken as the reinforcing material. The glass fiber cloth may be soaked with resin gel, and a heat treatment is performed to pre-bake the soaked cloth into a sheet. The sheet may be softened under heating and pressure, and may be cured and viscous after being cooled. In a high-temperature pressing process, the viscous sheet can bond to adjacent two layers. That is, the second insulation layer 17 is melted when being pressed at a high temperature to bond the first circuit layer 16 to the second circuit layer 18.

In the present embodiment, the groove 12 for receiving the chip 13 is groove running through two surfaces of the core board 11. In another embodiment, the groove 12 for receiving the chip 13 may alternatively be the blind groove running through one surface of the core board 11 as shown in FIG. 2. The second insulating layer 17 and the second circuit layer 18 are successively disposed on the outer side of the first circuit layer 16 near a side of the groove 12. The second lead terminal 19 is arranged with the second insulating layer 17 to electrically connect the first circuit layer 16 to the second circuit layer 18.

As shown in FIG. 4, FIG. 4 is a structural schematic view of a circuit board according to a fourth embodiment of the present disclosure. In the present embodiment, a third insulating layer 20 and a third circuit layer 21 are successively arranged on an outer side of the second circuit layer 18. The third insulating layer 20 defines a through-hole at a predetermined location. The conductive material is received in the through-hole to form a third lead terminal 22. The third lead terminal 22 is configured to connect the second circuit layer 18 to the third circuit layer 21.

It shall be understood that the third lead terminal 22 electrically connects the second circuit layer 18 to the third circuit layer 21, enabling the chip 13 to be electrically connected to the third circuit layer 21. In an embodiment, when a plurality of second circuit networks are arranged on the second circuit layer 18, and a plurality of third circuit networks are arranged on the third circuit layer 21, the third lead terminal 22 connects each of the second circuit networks on the second circuit layer 18 to each of the third circuit networks on the third circuit layer 21. In other words, any one of the second circuit networks is connected to any one of the third circuit networks, and each connection is achieved via one third lead terminal 22.

For example, the first circuit layer 16 is arranged with one first circuit network a, and one first lead terminal 14 connects the chip 13 to the first circuit network a. In this case, the number of first lead terminals 14 is 1.

In another example, when the first circuit layer 16 has the first circuit network a, and the second circuit layer 18 has a second circuit network a and a second circuit network b, one second lead terminal 19 connects the first circuit network a to the second circuit network a, and another second lead terminal 19 connects the first circuit network a to the second circuit network b. In this case, the number of second lead terminals 19 is two. Therefore, the number of second lead terminals 19 is n times of the number of first lead terminals 14, and then is an integer.

In another example, the second circuit layer 18 has a second circuit network a and a second circuit network b, and the third circuit layer 21 has a third circuit network a and a third circuit network b. One third lead terminal 22 connects the second circuit network a to the third circuit network a, another third lead terminal 22 connects the second circuit network b to the third circuit network a, still another third lead terminal 22 connects the second circuit network a to the third circuit network b, and still yet another third lead terminal 22 connects the second circuit network b to the third circuit network b. In this case, the number of third lead terminals 22 is 4. Therefore, the number of third lead terminals 22 is m times of the number of second lead terminals, and m is an integer.

In the present embodiment, material and specification of the third insulation layer 20 and the third circuit layer 21 are the same as those of the circuit layers and the insulation layers described in the above embodiments, and will not be repeated here.

As shown in FIG. 5, FIG. 5 is a flow chart of a method of manufacturing a circuit board according to a first embodiment of the present disclosure. The method includes following operations.

In an operation S41, a core board is provided.

In the present embodiment, the core board 11 is a copper-clad board, which is a basic material for manufacturing the circuit board. The copper-clad board includes a substrate board and a copper clad disposed on and covering the substrate board. The substrate board is a plurality of bonding sheets. Each of the plurality of bonding sheets is made by dipping a paper substrate, a glass fiber substrate, a synthetic fiber substrate, a non-woven substrate, a composite substrate and other materials in resin. The copper clad is coating on one side or two sides of the substrate board, and hot-press curing is performed, obtaining the copper-clad board. In an embodiment, the copper clad on each of two surfaces of the core board 11 may or may not have a circuit pattern layer, which may be determined based on demands and will not be limited by the present disclosure.

In an operation S42, a groove is defined in the core board.

The groove is defined at a predetermined location of the core board (i.e. a location where the chip is to be arranged). It shall be understood that a size the groove may be slightly greater than that of the core board in order to allow the chip to be received in the groove. Depending on specific requirements, the groove may be defined as a through groove running through two surfaces of the core board, or as a blind groove running through one surface of the core board.

In an operation S43, the chip is received in the groove, and the first lead terminal is exposed.

It shall be understood that, when the groove is the through groove, each of two sides of the chip has the first lead terminal. The chip is received in the groove (through groove), and the first lead terminal of the chip is exposed. When the groove is the blind groove, the first lead terminal may be arranged on one surface of the chip, and the surface arranged with the first lead terminal is placed towards a side of the core board that defines the groove. The first lead terminal may be arranged on each of two surfaces of the chip, and a side of the core board away from the groove defines a hole corresponding to a position where the first lead terminal is arranged. The first lead terminal is exposed through the hole.

In an operation S44, the first insulating layer defines a first through hole at a position corresponding to the first lead terminal.

The first insulating layer is arranged, and the first insulating layer defines the first through hole at the position corresponding to the first lead terminal.

In an operation S45, the first insulating layer and the first circuit layer are arranged successively on at least one side of the core board, such that the first lead terminal extends through the first through hole to be electrically connected to the first circuit layer.

The first insulating layer and the first circuit layer are disposed on an outside of the core board, and the first through hole of the first insulating layer is placed to correspond to the position of the first lead terminal. In this way, the first lead terminal extends through the first through hole to electrically connect the chip to the first circuit layer.

FIG. 6 is a flow chart of a method of manufacturing a circuit board according to a second embodiment of the present disclosure. In the present embodiment, the method further includes following operations.

In an operation S46, a second through hole is defined at a predetermined location of the second insulating layer, and a conductive layer is arranged inside the second through hole.

The second insulating layer is provided and defines the second through hole at the predetermined location. The predetermined location is a location where the second lead terminal is to be arranged. After the second through hole is defined, the conductive layer is arranged inside the second through hole to form the second lead terminal. The conductive layer may be a copper layer attached to a side wall of the second through hole or a copper post received in and filling the second through hole.

In an operation S47, a second insulating layer and a second circuit layer are successively arranged at the outside of the first circuit layer, such that the first circuit layer is electrically connected to the second circuit layer through the second through hole.

The second insulating layer is disposed on the outside of the first circuit layer, and the second circuit layer is arranged on a side of the second insulating layer away from the core board. The second lead terminal electrically connects the first circuit layer to the second circuit layer.

In an embodiment, when three circuit layers are arranged on the outside of the chip in the core board, the method further includes following operations.

In an operation S48, a third through hole is defined at a predetermined location in the third insulating layer, and a conductive layer is arranged inside the third through hole.

The third insulating layer is provided and defines the third through hole at the predetermined location. The predetermined location is a location where the third lead terminal is to be arranged. After the third through hole is defined, the conductive layer is arranged inside the third through hole to form the third lead terminal. The conductive layer may be a copper layer attached to a side wall of the third through hole or a copper post received in and filling the third through hole.

In an operation S49, a third insulating layer and a third circuit layer are successively arranged on the outside of the second circuit layer, such that the third circuit layer is electrically connected to the second circuit layer through the third through hole.

The third insulating layer is arranged on the outside of the second circuit layer. The third circuit layer is arranged on a side of the third insulating layer away from the core board. The third lead terminal electrically connects the second circuit layer to the third circuit layer.

According to the circuit board in the present disclosure, the groove is defined in the core board, and the chip is received in the groove, enabling the first lead terminal of the chip to connect to the first circuit layer. The second circuit layer is arranged on the outside of the first circuit layer, and the second lead terminal that connects to the first circuit layer and the second circuit layer is arranged. In this way, connection between the chip and the circuit is more flexible and convenient by increasing the number of connective pins.

The above is only an embodiment of the present disclosure and shall not be interpreted to limit the scope of the present disclosure. Any equivalent structure or equivalent process transformation based on the contents of the specification and accompanying drawings, applied directly or indirectly in other related fields, shall be equally covered by the present disclosure. 

What is claimed is:
 1. A circuit board, comprising: a core board, defining a groove; at least one chip, received in the groove, wherein the chip has a first lead terminal; a first circuit layer, arranged on at least one side of the core board; a first insulating layer, disposed between the core board and the first circuit layer; wherein the first lead terminal extends through the first insulating layer to be connected to the first circuit layer, enabling the chip to be electrically connected to the first circuit layer.
 2. The circuit board according to claim 1, further comprising: a second circuit layer, arranged on a side of the first circuit layer away from the core board; a second insulating layer, disposed between the first circuit layer and the second circuit layer; wherein the second insulating layer is configured with a second lead terminal to electrically connect the second circuit layer to the first circuit layer, enabling the chip to be electrically connected to the second circuit layer.
 3. The circuit board according to claim 2, further comprising: a third circuit layer, arranged on a side of the second circuit layer away from the core board; a third insulating layer, disposed between the second circuit layer and the third circuit layer; wherein the third insulating layer is configured with a third lead terminal to electrically connect the third circuit layer to the second circuit layer, enabling the chip to be electrically connected to the third circuit layer.
 4. The circuit board according to claim 1, wherein, the first circuit layer is arranged with a plurality of first circuit networks, the plurality of first circuit networks are different from each other; and the chip is electrically connected to the plurality of first line networks via different first lead terminals.
 5. The circuit board according to claim 3, wherein, the second circuit layer is arranged with a plurality of second circuit networks, the plurality of second circuit networks are different from each other; the second lead terminal electrically connects the first circuit networks, which are connected to the first lead terminals, to the second circuit network, enabling the chip to be electrically connected to the second circuit networks; the third circuit layer is arranged with a plurality of third circuit networks, the plurality of third circuit networks are different from each other; the third lead terminal electrically connects the second circuit networks, which are connected to the second lead terminal, to the third circuit networks, enabling the chip to be electrically connected to the third circuit networks.
 6. The circuit board according to claim 2, wherein the first circuit layer is arranged with a plurality of first circuit networks; and the second circuit layer is arranged with a plurality of second circuit networks.
 7. The circuit board according to claim 6, wherein the number of first circuit networks is equal to the number of second circuit networks.
 8. The circuit board according to claim 7, wherein the number of first lead terminal is equal to the number of second lead terminal.
 9. The circuit board according to claim 6, wherein the number of second circuit networks is n times of the number of first circuit networks.
 10. The circuit board according to claim 6, wherein the number of second lead terminals is n times the number of first lead terminals.
 11. The circuit board according to claim 5, wherein, the number of second lead terminals is n times of the number of first lead terminals, the n is an integer; the number of third lead terminals is m times of the number of second lead terminals, the m is an integer.
 12. The circuit board according to claim 6, wherein each of the first lead terminal, the second lead terminal and the third lead terminal is any one or a combination of a copper post or a conductive through hole.
 13. The circuit board according to claim 6, wherein a pad is arranged at each of two connective ends of the first lead terminal, each of two connective ends of the second lead terminal, and each of two connective ends of the third lead terminal.
 14. The circuit board according to claim 5, wherein any one of the second circuit networks is connected to any one of the third circuit networks, and each connection is achieved via one third lead terminal.
 15. The circuit board according to claim 1, wherein, the groove is a through groove running through two surfaces of the core board; or the groove is a blind groove running through one surface of the core board; wherein a distance between the chip and a side wall of the groove is 20 μm to 50 μm, and molding silicone is disposed between the chip and the side wall of the groove.
 16. The circuit board according to claim 3, wherein, a thickness of each of the first insulating layer, the second insulating layer, the third insulating layer, the first circuit layer, the second circuit layer and the third circuit layer is 10 μm to 40 μm.
 17. The circuit board according to claim 3, wherein, a thickness of each of the first insulating layer, the second insulating layer and the third insulating layer is 30 μm; and a thickness of each of the first circuit layer, the second circuit layer and the third circuit layer is 18 μm.
 18. The circuit board according to claim 3, wherein each of the first insulating layer, the second insulating layer and the third insulating layer are curable adhesive substance; and the core board is a copper-clad board.
 19. A method of manufacturing the circuit board, comprising: providing a core board; defining a groove in the core board; placing a chip in the groove and exposing a first lead terminal; defining a first through hole in a first insulating layer at a position corresponding to the first lead terminal; and arranging the first insulating layer and the first circuit layer successively on at least one side of the core board, allowing the first lead terminal to extend through the first through hole to be electrically connected to the first circuit layer.
 20. The method according to claim 19, further comprising: defining a second through hole in a second insulating layer at a predetermined position, and arranging a conductive layer in the second through hole; arranging a second insulating layer and a second circuit layer successively on an outside of the first circuit layer, allowing the first circuit layer to be electrically connected to the second circuit layer through the second through hole; defining a third through hole at a predetermined position in the third insulating layer, and arranging a conductive layer in the third through hole; and arranging a third insulating layer and a third circuit layer successively on an outside of the second circuit layer, allowing the third circuit layer to be electrically connected to the second circuit layer through the third through hole. 